MC68HC912BD32 Datasheet, PDF (105/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Clocks
Clock Functions
Table 19 Slow Mode Register Divider Rates
SLDV2 SLDV1 SLDV0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Divder
(2^x )
Off
2
4
8
16
32
64
128
Bus Rate
Bus Rate
Bus Rate
(16 MHz Oscillator) (32 MHz Oscillator) (40 MHz Oscillator)
4 MHz
8 MHz
20 MHz
2 MHz
4 MHz
10 MHz
1 MHz
2 MHz
5 MHz
500 kHz
1 MHz
2.5 MHz
250 kHz
500 kHz
1.25 MHz
125 kHz
250 kHz
625 kHz
62.5 kHz
125 kHz
312 kHz
31.2 kHz
62.5 kHz
156 kHz
Clock Functions
The clock generation module generates and controls the timing of the
reset and power-on reset logic.
Computer Operating Properly (COP)
The COP or watchdog timer is an added check that a program is running
and sequencing properly. When the COP is being used, software is
responsible for keeping a free-running watchdog timer from timing out. If
the watchdog timer times out it is an indication that the software is no
longer being executed in the intended sequence; thus a system reset is
initiated. Three control bits allow selection of seven COP time-out
periods or COP disable. When COP is enabled, sometime during the
selected period the program must write $55 and $AA (in this order) to the
COPRST register. If the program fails to do this the part will reset. If any
value other than $55 or $AA is written to COPRST, the part is reset.
5-clock
Clocks
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MC68HC912BD32 Rev 1.0