MC68HC912BD32 Datasheet, PDF (215/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
Programmer’s Model
LOCKIE — Locking Error Interrupt Enable
1 = A locking error will result in a general interrupt and the module
will enter soft reset.
0 = No interrupt will be generated from this event and the module
does not enter soft reset.
NOTE: The LOCKIE bit can only be written if the SFTRES bit in the Module
Configuration register is set.
WAKEIE — WAKEUP Interrupt Enable
1 = A requested wake-up will result in a general interrupt.
0 = No interrupt will be generated from this event.
Receive Interrupt
Vector Register
(RIVEC)
The read-only Receive Interrupt Vector Register shows the lowest
numbered message buffer that has its interrupt status flag (IFLG) and its
interrupt enable bit (IENA) set. A hard or soft reset will clear the register.
RIVEC
R
$xx0A
W
H/S-RESET
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
RIVEC3
BIT 2
RIVEC2
BIT 1
RIVEC1
0
0
0
0
0
0
0
Figure 46 Receive Interrupt Source Register (RIVEC)
BIT 0
RIVEC0
0
NOTE: The Receive Interrupt Vector Register contains only valid data if RXIF is
set.
Transmit Interrupt
Vector Register
(TIVEC)
The read-only Transmit Interrupt Vector Register shows the highest
numbered message buffer that has its interrupt status flag (IFLG) and its
interrupt enable bit (IENA) set. A hard or soft reset will clear the register.
TIVEC
R
$xx0B
W
H/S-RESET
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
TIVEC3
BIT 2
TIVEC2
BIT 1
TIVEC1
0
0
0
0
1
1
1
Figure 47 Transmit Interrupt Source Register (TIVEC)
BIT 0
TIVEC0
1
NOTE: The Transmit Interrupt Vector Register contains only valid data if TXIF is
set.
45-sibus
Byteflight™ Module
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MC68HC912BD32 Rev 1.0