MC68HC912BD32 Datasheet, PDF (226/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Analog to Digital Converter
Because the bias currents to the analog circuits are turned off, the
ATD requires a period of recovery time to stabilize the analog circuits
after setting the ADPU bit.
AFFC — ATD Fast Flag Clear All
0 = ATD flag clearing operates normally (read the status register
before reading the result register to clear the associate CCF
bit).
1 = Changes all ATD conversion complete flags to a fast clear
sequence. Any access to a result register (ATD0–7) will cause
the associated CCF flag to clear automatically if it was set at
the time.
AWAI — ATD Stop in Wait Mode
0 = ATD continues to run when the MCU is in wait mode
1 = ATD stops to save power when the MCU is in wait mode
ASCIE — ATD Sequence Complete Interrupt Enable
0 = Disables ATD interrupt
1 = Enables ATD interrupt on sequence complete
ASCIF — ATD Sequence Complete Interrupt
Cannot be written in any mode.
0 = No ATD interrupt occurred
1 = ATD sequence complete
ATDCTL3 — ATD Control Register 3
Bit 7
6
5
4
3
2
1
0
0
0
0
0
0
FRZ1
RESET:
0
0
0
0
0
0
0
Bit 0
FRZ0
0
$0063
FRZ1, FRZ0 — Background Debug (Freeze) Enable (suspend module
operation at breakpoint)
When debugging an application, it is useful in many cases to have the
ATD pause when a breakpoint is encountered. These two bits
determine how the ATD will respond when background debug mode
becomes active.
MC68HC912BD32 Rev 1.0
Analog to Digital Converter
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Go to: www.freescale.com
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