MC68HC912BD32 Datasheet, PDF (243/292 Pages) Freescale Semiconductor, Inc – Advance Information

BDM Lockout
Freescale Semiconductor, Inc.
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Background Debug Mode
data read commands, the host must insert this delay between sending
the address and attempting to read the data.In the case of a write
command, the host must delay after the data portion, before sending a
new command, to be sure the write has finished.
The external host should delay about 32 target BCLK cycles between a
firmware read command and the data portion of these commands. This
allows the BDM firmware to execute the instructions needed to get the
requested data into the BDM SHIFTER register.
The external host should delay about 32 target BCLK cycles after the
data portion of firmware write commands to allow BDM firmware to
complete the requested write operation before a new serial command
disturbs the BDM SHIFTER register.
The external host should delay about 64 target BCLK cycles after a
TRACE1 or GO command before starting any new serial command. This
delay is needed because the BDM SHIFTER register is used as a
temporary data holding register during the exit sequence to user code.
BDM logic retains control of the internal buses until a read or write is
completed.If an operation can be completed in a single cycle, it does not
intrude on normal CPU12 operation.However, if an operation requires
multiple cycles, CPU12 clocks are frozen until the operation is complete.
The access to the MCU resources by BDM may be prevented by
enabling the BDM lockout feature. When enabled, the BDM lockout
mechanism prevents the BDM from being active. In this case the BDM
ROM is disabled and does not appear in the MCU memory map.
The BDM lockout is enabled by clearing NOBDML bit of EEMCR
register. The NOBDML bit is loaded at reset from the SHADOW byte of
EEPROM module. Modifying the state of the NOBDML and
corresponding EEPROM SHADOW bit is only possible in special modes.
Please refer to EEPROM for NOBDML information.
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MC68HC912BD32 Rev 1.0