MC68HC912BD32 Datasheet, PDF (148/292 Pages) Freescale Semiconductor, Inc – Advance Information

Serial Interface
Freescale Semiconductor, Inc.
Block diagram
RxD
PS0
SERIAL
SCI
INTERFACE
TxD
PS1
I/O
PS2
I/O
I/O
PS3
MISO/SISO
PS4
MOSI/MOMI
PS5
SPI
SCK
PS6
CS/SS
PS7
Figure 19 Serial Interface Block Diagram
Serial Communication Interface (SCI)
The serial communication interface on the MC68HC912BD32 is an NRZ
format (one start, eight or nine data, and one stop bit) asynchronous
communication system with independent internal baud rate generation
circuitry and an SCI transmitter and receiver. It can be configured for
eight or nine data bits (one of which may be designated as a parity bit,
odd or even). If enabled, parity is generated in hardware for transmitted
and received data. Receiver parity errors are flagged in hardware. The
baud rate generator is based on a modulus counter, allowing flexibility in
choosing baud rates. There is a receiver wake-up feature, an idle line
detect feature, a loop-back mode, and various error detection features.
Two port pins provide the external interface for the transmitted data
(TXD) and the received data (RXD).
MC68HC912BD32 Rev 1.0
2-sint
Serial Interface
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