MC68HC912BD32 Datasheet, PDF (152/292 Pages) Freescale Semiconductor, Inc – Advance Information

Serial Interface
Freescale Semiconductor, Inc.
SC0CR1 — SCI Control Register 1
Bit 7
6
5
4
3
2
LOOPS WOMS RSRC
M
WAKE
ILT
RESET:
0
0
0
0
0
0
$00C2
1
Bit 0
PE
PT
0
0
Read or write anytime.
LOOPS — SCI LOOP Mode/Single Wire Mode Enable
0 = SCI transmit and receive sections operate normally.
1 = SCI receive section is disconnected from the RXD pin and the
RXD pin is available as general purpose I/O. The receiver input
is determined by the RSRC bit. The transmitter output is
controlled by the associated DDRS bit. Both the transmitter
and the receiver must be enabled to use the LOOP or the
single wire mode.
If the DDRS bit associated with the TXD pin is set during the LOOPS
= 1, the TXD pin outputs the SCI waveform. If the DDRS bit
associated with the TXD pin is clear during the LOOPS = 1, the TXD
pin becomes high (IDLE line state) for RSRC = 0 and high impedance
for RSRC = 1. Refer to Table 30.
WOMS — Wired-Or Mode for Serial Pins
This bit controls the two pins (TXD and RXD) associated with the SCI
section.
0 = Pins operate in a normal mode with both high and low drive
capability. To affect the RXD bit, that bit would have to be
configured as an output (via DDRS) which is the single wire case
when using the SCI. WOMS bit still affects general purpose
output on TXD and RXD pins when SCI is not using these pins.
1 = Each pin operates in an open drain fashion if that pin is
declared as an output.
RSRC — Receiver Source
When LOOPS = 1, the RSRC bit determines the internal feedback
path for the receiver.
0 = Receiver input is connected to the transmitter internally (not
TXD pin)
1 = Receiver input is connected to the TXD pin
MC68HC912BD32 Rev 1.0
6-sint
Serial Interface
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