MC68HC912BD32 Datasheet, PDF (179/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
Byteflight™ Protocol
Table 34 Parameter of the Byteflight™ System
Symbol
Characteristic
t_wx
message idle time
Description
Typ
time between the end of the Sync pulse or end of the
previous message and the start of the transmitted
message.
t_wx >= t_idle_min
t_wx = twx0_tx + twx_delta * (ID - IDx-1), when the
node sent the last activity on the bus
t_wx = twx0_rx + twx_delta * (ID - IDx-1), when the
node received the last activity on the bus
t_wx0_tx
constant part of t_wx when
last bus activity was
transmitted
t_wx0_tx can be programmed individually for each
node in the register TCR1
<1900ns
t_wx0_rx
constant part of t_wx when
last bus activity was
received
t_wx0_rx can be programmed individually for each
node in the register TCR2
<1900ns
t_latest_tx
latest start of transmit
t_latest_tx is currently hard wired
229.0 µs
t_start_seq_tx length of tx start sequence t_start_seq_tx is currently hard wired
600ns
t_start_seq_rx
length of rx start sequence
(max)
t_start_seq_rx is currently hard wired
975ns
t_start_seq_rx
length of rx start sequence
(min)
t_start_seq_rx is currently hard wired
100ns
t_wx_delta multiplier part of t_wx
this value must be assigned identically for each node
using register TCR3. t_wx_delta = t_max +
t_tolerance
< 1200ns
> 200ns
t_recognize
recognition time for bus
activity
time required for recognition of bus activity: time
from falling edge of RX pin until the bus controller
can stop a waiting transmit process
<125ns
t_wake_up
length of wake up pulse
a sequence of dominant and recessive pulses of
length t_wake_up is sent out if WPULSE is set
6.4 µs
1. 249.75µs<=t_cyc<=250.25µs in 100% of cases there is no error, t_cyc<249.7µs or t>250.3µs in 100% of cases sync too
early/ lost
2. 1.875µs<=t_syn_a<=2.125µs in 100% of cases sync alarm is accepted, t_syn_a<1.825µs or t_syn_a>2.175µs in 100% of
sync alarm is not accepted, but illegal pulse is detected
3. 2.875µs<=t_syn_n<=3.125µs in 100% of cases sync normal is accepted, t_syn_n<2.825µs or t_syn_n>3.175µs in 100%
of sync normal is not accepted, but illegal pulse is detected
9-sibus
Byteflight™ Module
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MC68HC912BD32 Rev 1.0