MC68HC912BD32 Datasheet, PDF (75/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Flash EEPROM
Operation
Table 1 Effects of ENPE, LAT and ERAS on Array Reads
ENPE LAT ERAS
Result of Read
0
0
– Normal read of location addressed
0
1
0 Read of location being programmed
0
1
1 Normal read of location addressed
1
–
– Read cycle is ignored
Operation
The Flash EEPROM can contain program and data. On reset, it can
operate as a bootstrap memory to provide the CPU with internal
initialization information during the reset sequence.
Bootstrap
Operation
Single-Chip Mode
After reset, the CPU controlling the system will begin booting up by
fetching the first program address from address $FFFE.
Normal Operation
The Flash EEPROM allows a byte or aligned word read/write in one bus
cycle. Misaligned word read/write require an additional bus cycle. The
Flash EEPROM array responds to read operations only. Write
operations are ignored.
Program/Erase
Operation
An unprogrammed Flash EEPROM bit has a logic state of one. A bit
must be programmed to change its state from one to zero. Erasing a bit
returns it to a logic one. The Flash EEPROM has a minimum
program/erase life of 100 cycles. Programming or erasing the Flash
EEPROM is accomplished by a series of control register writes and a
write to a set of programming latches.
Programming is restricted to a single byte or aligned word at a time as
determined by internal signal SZ8 and ADDR[0]. The Flash EEPROM
must first be completely erased prior to programming final data values.
It is possible to program a location in the Flash EEPROM without erasing
7-flash
Flash EEPROM
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MC68HC912BD32 Rev 1.0