MC68HC912BD32 Datasheet, PDF (73/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Flash EEPROM
Flash EEPROM Registers
STRE — Spare Test Row Enable
The spare test row consists of one Flash EEPROM array row. The
reserved word at location 31 contains production test information
which must be maintained through several erase cycles. When STRE
is set, the decoding for the spare test row overrides the address lines
which normally select the other rows in the array.
0 = LIB accesses are to the Flash EEPROM array
1 = Spare test row in array enabled if SMOD is active
MWPR — Multiple Word Programming
Used primarily for testing, if MPWR = 1, the two least-significant
address lines ADDR[1:0] will be ignored when programming a Flash
EEPROM location. The word location addressed if ADDR[1:0] = 00,
along with the word location addressed if ADDR[1:0] = 10, will both be
programmed with the same word data from the programming latches.
This bit should not be changed during programming.
0 = Multiple word programming disabled
1 = Program 32 bits of data
FEECTL — Flash EEPROM Control Register
$00F7
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
FEESWAI SVFP
ERAS
LAT
ENPE
RESET:
0
0
0
0
0
0
0
0
This register controls the programming and erasure of the Flash
EEPROM.
FEESWAI — Flash EEPROM Stop in Wait Control
0 = Do not halt Flash EEPROM clock when the part is in wait mode.
1 = Halt Flash EEPROM clock when the part is in wait mode.
NOTE: The FEESWAI bit cannot be asserted if the interrupt vector resides in the
Flash EEPROM array.
SVFP — Status V_FP Voltage
SVFP is a read only bit.
0 = Voltage of V_FP pin is below normal programming voltage levels
1 = Voltage of V_FP pin is above normal programming voltage levels
5-flash
Flash EEPROM
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MC68HC912BD32 Rev 1.0