MC68HC912BD32 Datasheet, PDF (191/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
Low Power Modes
Module Sleep
Mode
The CPU can request the Byteflight™ to enter this low-power mode by
asserting the SLPRQ bit in the Module Configuration Register. The time
when the Byteflight™ enters Sleep Mode depends on its activity:
• if it is transmitting, it continues to transmit until there is no more
message to be transmitted, and then goes into Sleep Mode.
• if it is receiving, it waits for the end of this message and then goes
into Sleep Mode.
• if it is neither transmitting nor receiving, it immediately goes into
Sleep Mode.
NOTE:
The application software must avoid setting up a transmission (by
clearing one or more IFLG flag(s)) and immediately request Sleep Mode
(by setting SLPRQ). It then depends on the exact sequence of
operations whether the Byteflight™ starts transmitting or goes into Sleep
Mode directly. The application software should use SLPAK as a
handshake indication for the request (SLPRQ) to go into Sleep Mode.
During Sleep Mode, the SLPAK flag is set. When in Sleep Mode, the
Byteflight™ stops its internal clocks. However, clocks to allow register
accesses still run. The Tx pin stays in recessive state. It is possible to
access locked transmit and receive buffers but no message abort and
buffer lock/unlock takes place while in sleep mode.
The Byteflight™ leaves Sleep Mode (wake-up) when
• bus activity occurs or
• the MCU clears the SLPRQ or
• the MCU sets SFTRES.
NOTE: The MCU cannot clear the SLPRQ bit before the Byteflight™ is in Sleep
Mode (SLPAK = 1).
After wake-up, the Byteflight™ waits for a sync pulse to synchronize to
the bus. As a consequence, if the Byteflight™ is woken-up by a valid
message, this message is not received. The receive message buffer
content is not affected by sleep-mode. All pending actions are executed
upon wake-up: message aborts, buffer lock and message
transmissions.
21-sibus
Byteflight™ Module
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MC68HC912BD32 Rev 1.0