MC68HC912BD32 Datasheet, PDF (230/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Analog to Digital Converter
Table 54 Multichannel Mode Result Register Assignment
S8CM CD
CC
CB
CA
Channel Signal
Result in ADRx
if MULT = 1
1
0
0
0
0
AN0
ADR0
0
0
1
AN1
ADR1
0
1
0
AN2
ADR2
0
1
1
AN3
ADR3
1
0
0
AN4
ADR4
1
0
1
AN5
ADR5
1
1
0
AN6
ADR6
1
1
1
AN7
ADR7
1
1
0
0
0
Reserved
ADR0
0
0
1
Reserved
ADR1
0
1
0
Reserved
ADR2
0
1
1
Reserved
ADR3
1
0
0
V_RH
ADR4
1
0
1
V_RL
ADR5
1
1
0
(V_RH + V_RL)/2
ADR6
1
1
1
TEST/Reserved
ADR7
Shaded bits are “don’t care” if MULT = 1 and the entire block of four or eight channels make up
a conversion sequence. When MULT = 0, all four bits (CD, CC, CB, and CA) must be specified
and a conversion sequence consists of four or eight consecutive conversions of the single
specified channel.
ATDSTAT — ATD Status Register
Bit 7
6
5
4
SCF
0
0
0
RESET:
0
0
0
0
$0066
3
2
1
Bit 0
0
CC2
CC1
CC0
0
0
0
0
ATDSTAT — ATD Status Register
RESET:
Bit 7
CCF7
0
6
CCF6
0
5
CCF5
0
4
CCF4
0
3
CCF3
0
2
CCF2
0
1
CCF1
0
Bit 0
CCF0
0
$0067
The ATD status registers contain the flags indicating the completion of
ATD conversions.
Normally, it is read-only. In special mode, the SCF bit and the CCF bits
may also be written.
MC68HC912BD32 Rev 1.0
Analog to Digital Converter
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