MC68HC912BD32 Datasheet, PDF (150/292 Pages) Freescale Semiconductor, Inc – Advance Information

Serial Interface
Freescale Semiconductor, Inc.
SCI Baud Rate
Generation
• Data that is transmitted or received least significant bit (LSB) first.
• A stop bit (logic one), used to indicate the end of a frame. (A frame
consists of a start bit, a character of eight or nine data bits and a
stop bit.)
• A BREAK is defined as the transmission or reception of a logic
zero for one frame or more.
• This SCI supports hardware parity for transmit and receive.
The basis of the SCI baud rate generator is a 13-bit modulus counter.
This counter gives the generator the flexibility necessary to achieve a
reasonable level of independence from the CPU operating frequency
and still be able to produce standard baud rates with a minimal amount
of error. The clock source for the generator comes from the P Clock.
Table 29 Baud Rate Generation
Desired
SCI Baud Rate
110
300
600
1200
2400
4800
9600
14400
19200
38400
BR Divisor for
P = 4.0 MHz
2273
833
417
208
104
52
26
17
13
—
BR Divisor for
P = 8.0 MHz
4545
1667
833
417
208
104
52
35
26
13
BR Divisor for
P = 10.0 MHz
5682
2083
1042
521
260
130
65
43
33
16
Register
Descriptions
Control and data registers for the SCI subsystem are described below.
The memory address indicated for each register is the default address
that is in use after reset. The entire 512-byte register block can be
mapped to any 2K byte boundary within the standard 64K byte address
space.
MC68HC912BD32 Rev 1.0
4-sint
Serial Interface
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