MC68HC912BD32 Datasheet, PDF (228/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Analog to Digital Converter
ATD module clock. The divide-by-two circuit insures symmetry of the
output clock signal. Clearing these bits causes the prescale value
default to one which results in a ÷2 prescale factor. This signal is then
fed into the ÷2 logic. The reset state divides the P clock by a total of
four and is appropriate for nominal operation between 2 MHz and 8
MHz bus rate. For operation at 10 MHz this value must be
reprogrammed first to ÷6 or greater before using the ATD. Table 53
shows the divide-by operation and the appropriate range of system
clock frequencies.
Table 53 Clock Prescaler Values
Prescale Value Total Divisor
00000
÷2
00001
÷4
00010
÷6
00011
÷8
00100
÷10
00101
÷12
00110
÷14
00111
÷16
01xxx
1xxxx
Max P Clock⁽¹⁾
4 MHz
8 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
Do Not Use
Min P Clock⁽²⁾
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
7 MHz
8 MHz
1. Maximum conversion frequency is 2 MHz. Maximum P clock divisor value will become
maximum conversion rate that can be used on this ATD module.
2. Minimum conversion frequency is 500 KHz. Minimum P clock divisor value will become
minimum conversion rate that this ATD can perform.
ATDCTL5 — ATD Control Register 5
$0065
Bit 7
6
5
4
3
2
1
Bit 0
0
S8CM
SCAN
MULT
CD
CC
CB
CA
RESET:
0
0
0
0
0
0
0
0
The ATD control register 5 is used to select the conversion modes,
the conversion channel(s), and initiate conversions.
Read or write anytime. A write to ATDCTL5 initiates a new conversion
sequence. If a conversion sequence is in progress when a write
occurs, that sequence is aborted and the SCF and CCF bits are reset.
S8CM — Select 8 Channel Mode
MC68HC912BD32 Rev 1.0
Analog to Digital Converter
For More Information On This Product,
Go to: www.freescale.com
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