MC68HC912BD32 Datasheet, PDF (247/292 Pages) Freescale Semiconductor, Inc – Advance Information

INSTRUCTION –
Hardware
Instruction
Decode
Freescale Semiconductor, Inc.
Development Support
Background Debug Mode
CLKSW — Clock Switch
0 = BDM system operates with BCLK.
1 = BDM system operates with ECLK.
The WRITE_BD_BYTE@FF01 command that changes CLKSW
including 150 cycles after the data portion of the command should be
timed at the old speed. Beginning with the start of the next BDM
command, the new clock can be used for timing BDM
communications.
If ECLK rate is slower than BCLK rate, CLKSW is ignored and BDM
system is forced to operate with ECLK.
The INSTRUCTION register is written by the BDM hardware as a result
of serial data shifted in on the BKGD pin. It is readable and writable in
Special Peripheral mode on the parallel bus. It is discussed here for two
conditions: when a hardware command is executed and when a
firmware command is executed.
Read and write: all modes
. The hardware clears the INSTRUCTION register if 512 BCLK cycles
occur between falling edges from the host.
INSTRUCTION — BDM Instruction Register (hardware command explanation)
BIT 7
6
5
4
3
2
1
BIT 0
H/F
DATA
R/W
BKGND
W/B
BD/U
0
0
RESET:
0
0
0
0
0
0
0
0
$FF00
The bits in the BDM instruction register have the following meanings
when a hardware command is executed.
H/F — Hardware/Firmware Flag
0 = Firmware command
1 = Hardware command
DATA — Data Flag – Shows that data accompanies the command.
0 = No data
1 = Data follows the command
13-dev
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MC68HC912BD32 Rev 1.0