MC68HC912BD32 Datasheet, PDF (28/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Pinout and Signal Descriptions
should be latched at the rising edge of E. To allow for maximum address
setup time at external devices, a transparent latch should be used.
Read/Write (R/W)
In all modes this pin can be used as I/O and is a general-purpose input
with an active pull-up out of reset. If the read/write function is required it
should be enabled by setting the RDWE bit in the PEAR register.
External writes will not be possible until enabled.
Low-Byte Strobe
(LSTRB)
In all modes this pin can be used as I/O and is a general-purpose input
with an active pull-up out of reset. If the strobe function is required, it
should be enabled by setting the LSTRE bit in the PEAR register. This
signal is used in write operations and so external low byte writes will not
be possible until this function is enabled. This pin is also used as TAGLO
in Special Expanded modes and is multiplexed with the LSTRB function.
Instruction Queue
Tracking Signals
(IPIPE1 and IPIPE0)
These signals are used to track the state of the internal instruction
execution queue. Execution state is time-multiplexed on the two signals.
Refer to Development Support.
Data Bus Enable
(DBE)
The DBE pin (PE7) is an active low signal that will be asserted low during
E-clock high time. DBE provides separation between output of a
multiplexed address and the input of data. When an external address is
stretched, DBE is asserted during what would be the last quarter cycle
of the last E-clock cycle of stretch. In expanded modes this pin is used
to enable the drive control of external buses during external reads. Use
of the DBE is controlled by the NDBE bit in the PEAR register. DBE is
enabled out of reset in expanded modes. This pin has an active pullup
during and after reset in single chip modes.
Clock Divider
Bypass (DIVBYP)
This feature is intended for test purposes only. The DIVBYP pin is input
only. The logic state of this static signal is active high. There is an active
pull-down on this pin to disable the clock divider bypass when left open.
For application it is recommended to tie DIVBYP to VSS. The E-clock
rate is 1/4 of the frequency applied to EXTAL.
MC68HC912BD32 Rev 1.0
Pinout and Signal Descriptions
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