MC68HC912BD32 Datasheet, PDF (176/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
Every transmitted message contains an additional message start
sequence of 6 bits logic ‘0’ followed by the startbit (‘1’) of the first byte.
The receiver must recognize at least one bit (‘0’) of the start sequence
and the following startbit (‘1’).
IDLE
t_syn_n
t_w0
t_wx
t_cyc
t_syn_a
t_cyc
t_syn_n
Figure 29 Byteflight™ Cycle Timing
The current bus master generates periodic synchronization (SYNC)
pulses in the cycle of t_cyc. There are two types of SYNC pulses, the
normal SYNC pulse with a duration of t_syn_n and the ALARM pulse
with the duration of t_syn_a.
Every node can be configured as bus master by software. In the
Byteflight™ system only one bus master should exist. All other nodes
are bus slaves and use the SYNC pulses for their internal
synchronization. The bus master and the bus slaves can send and
receive messages in the communication cycle, which is the time
between the SYNC pulses.
The order of the messages is determined by their priorities which are
given by their identifiers ID (highest priority = lowest identifier). Every
identifier can appear only once during a cycle. This warrants that a
certain amount of high priority messages can be transferred, the bus
cannot be occupied by the message with the highest priority.
Based on TCR1, TCR2, TCR3 (Table 34) a slot counter is running after
a sync pulse was transmitted (master) or received (slave).
Master:
From sync pulse: TCR1 + TCR3: slot counter becomes 1
From sync pulse: TCR1 + 2*TCR3: slot counter becomes 2
Form sync pulse: TCR1 + 3*TCR3: slot counter becomes 3
MC68HC912BD32 Rev 1.0
Byteflight™ Module
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6-sibus