MC68HC912BD32 Datasheet, PDF (210/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
1 = SYNC pulse NORMAL has been received.
0 = No SYNC pulse NORMAL has occurred.
SLMMIF — Slot Mismatch Interrupt Flag
This bit will be set when the identifier of a successfully received
message differs from the current time slot.
1 = A mismatch between successfully received identifier and slot
counter has occurred.
0 = No slot mismatch has occurred.
XSYNIF — XSYNC Pulse Interrupt Flag
This bit will be set when a valid SYNC pulse (NORMAL or ALARM
Sync pulse) has been received. If enabled, an XSYNC pulse interrupt
is pending while the flag is set.
1 = SYNC pulse has been received.
0 = No SYNC pulse has occurred.
OPTDF — Optical Diagnosis Flag
This bit will be set when the internal error bit of the optical transceiver
is driven on the Rx line during transmission.
1 = A pulse on Rx has been detected.
0 = No pulse on Rx has been detected.
General Interrupt
Status Register
(GISR)
The General Interrupt Status Register indicates the occurrence of
system events, and together with the General Interrupt Enable Register
allows the module to operate in a polled or interrupt driven system. A
general interrupt can be generated.
OVRNIF, ERRIF, SYNEIF, SYNLIF, ILLPIF and WAKEIF are read and
clear only. TXIF and LOCKIF are read only. A flag can be cleared by
writing a 1 to the corresponding bit position. Only one write is necessary
to request the clearing, i.e. the clear request is stored and excuted as
soon as the condition which caused the setting is no longer valid.
SYNLIF can only cleared after receiving a valid sync pulse. Writing a 0
has no effect on the flag setting. Every flag has an associated interrupt
enable bit in the General Interrupt Enable Register. A hard or soft reset
will clear the register (except LOCKIF, which can only be cleared by a
hard or system reset).
MC68HC912BD32 Rev 1.0
Byteflight™ Module
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