MC68HC912BD32 Datasheet, PDF (218/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
Module Version
Register (MVR)
The read-only Module Version Register contains the version number of
the implementation.
MVR
$xx0E
BIT 7
R MVR7
W
BIT 6
MVR6
BIT 5
MVR5
BIT 4
MVR4
BIT 3
MVR3
BIT 2
MVR2
Figure 51 Module Version Register (MVR)
BIT 1
MVR1
BIT 0
MVR0
Byteflight™ Port
SBI Control
Register (PCTLSBI)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
PCTLSBI R
0
PMEREN
PSLMEN PERREN PROKEN PSYNEN
$xx10
W
HARDRESET
0
0
0
0
0
0
Figure 52 Port SBI Control Register (PCTLSBI)
BIT 1
PUESBI
0
BIT 0
RDRSBI
0
The following bits control pins of Port SBI. Pins 1 and 0 are reserved
for the Rx (input only) and Tx (output only) pins. Only a hard reset will
clear the register.
PMEREN — Slot Mismatch Error Enable
1 = A 50ns pulse is driven on Port SBI4 after a slot mismatch.
0 = Port SBI4 is a general IO pin.
PSLMEN — Slot Mismatch Enable
1 = A 50ns pulse is driven on Port SBI5 after a slot mismatch.
0 = Port SBI5 is a general IO pin.
PERREN — Error Pulse Enable
1 = A 50ns pulse is driven on Port SBI4 after a message format or
illegal pulse error.
0 = Port SBI4 is a general IO pin.
PROKEN — Reception OK Pulse Enable
1 = A 50ns pulse is driven on Port SBI3 after the successful
reception of a message or sync pulse.
0 = Port SBI3 is a general IO pin.
MC68HC912BD32 Rev 1.0
Byteflight™ Module
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48-sibus