MC68HC912BD32 Datasheet, PDF (113/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Pulse Width Modulator
Pulse Width Modulator
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
PWM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
PWM Boundary Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Introduction
1-pwm
The pulse-width modulator (PWM) subsystem provides four
independent 8-bit PWM waveforms or two 16-bit PWM waveforms or a
combination of one 16-bit and two 8-bit PWM waveforms. Each
waveform channel has a programmable period and a programmable
duty-cycle as well as a dedicated counter. A flexible clock select scheme
allows four different clock sources to be used with the counters. Each of
the modulators can create independent, continuous waveforms with
software-selectable duty rates from 0 percent to 100 percent. The PWM
outputs can be programmed as left-aligned outputs or center-aligned
outputs.
The four PWM channel outputs share general-purpose port P pins.
Enabling PWM pins takes precedence over the general-purpose port.
When PWM are not in use, the port pins may be used for discrete
input/output.
The period and duty registers are double buffered so that if they change
while the channel is enabled, the change will not take effect until the
counter reaches zero or the channel is disabled and then re-enabled. If
the channel is not enabled then writes to the period and/or duty register
will go only to the shadow latches. When the channel is enabled
(PWENx) is written from 0 to 1) the counter direction is set to UP and the
Shadow to Register transfer for PWPERx and PWDTYx is done.
Pulse Width Modulator
For More Information On This Product,
Go to: www.freescale.com
MC68HC912BD32 Rev 1.0