MC68HC912BD32 Datasheet, PDF (64/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Bus Control and Input/Output
alternate control function is selected, the associated DDRE bits are
overridden.
The reset condition of this register depends on the mode of operation
because bus-control signals are needed immediately after reset in some
modes.
In normal single-chip mode, no external bus control signals are needed
so all of port E is configured for general-purpose I/O.
In special single-chip mode, the E clock is enabled as a timing reference
and the other bits of port E are configured for general-purpose I/O.
In normal expanded modes, the reset vector is located in external
memory. The E clock may be required for this access but R/W is only
needed by the system when there are external writable resources.
Therefore in normal expanded modes, only the E clock is configured for
its alternate bus control function and the other bits of port E are
configured for general-purpose I/O. If the normal expanded system
needs any other bus-control signals, PEAR would need to be written
before any access that needed the additional signals.
In special expanded modes, IPIPE1, IPIPE0, E, R/W, and LSTRB are
configured as bus-control signals.
In peripheral mode, the PEAR register is not accessible for reads or
writes.
NDBE — No Data Bus Enable
Read and write anytime.
0 = PE7 is used for external control of data enables on memories.
1 = PE7 is used for general-purpose I/O.
PIPOE — Pipe Signal Output Enable
Normal: write once; Special: write anytime except the first time. Read
anytime.This bit has no effect in single chip modes.
0 = PE[6:5] are general-purpose I/O.
1 = PE[6:5] are outputs and indicate the state of the instruction
queue.
MC68HC912BD32 Rev 1.0
Bus Control and Input/Output
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6-bus