MC68HC912BD32 Datasheet, PDF (127/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Pulse Width Modulator
PWM Register Description
PSBCK — PWM Stops while in Background Mode
0 = Allows PWM to continue while in background mode. This is
useful for emulation.
1 = Disable PWM input clock when the part is in background mode.
PWTST— PWM Special Mode Register (“Test”)
$0055
Bit 7
6
5
4
3
2
1
Bit 0
DISCR DISCP DISCAL
0
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
Read anytime but write only in Special mode (SMOD = 1). These bits
are available only in Special mode and are reset in Normal mode.
The PWM has some special test functions which are only accessible
when the device is in Special Mode. Special Mode is indicated to the
PWM module when the SMOD line on the LIB is asserted.
When the SMOD line is asserted, the Special Mode register control
bits are accessed via the LIB. When SMOD is not asserted, writes to
the Special Mode control bits have no effect ana all bits in the Special
Mode register are forced to 0. This ensures that the PWM Special
Mode can not be invoked inadvertently during normal operation.
DISCR — Disable Reset of Channel Counter on Write to Channel
Counter
0 = Normal operation. Write to PWM channel counter will reset
channel counter.
1 = Write to PWM channel counter does not reset channel counter.
DISCP — Disable Compare Count Period
0 = Normal Operation
1 = In Left-Aligned Output mode, match of period does not reset the
associated PWM counter register.
DISCAL — Disable load of Scale-counters on write to the associated
scale-registers
0 = Normal Operation
1 = Write to PWSCAL0 and PWSCAL1 does not load scale
counters
15-pwm
Pulse Width Modulator
For More Information On This Product,
Go to: www.freescale.com
MC68HC912BD32 Rev 1.0