MC68HC912BD32 Datasheet, PDF (104/292 Pages) Freescale Semiconductor, Inc – Advance Information

Clocks
Freescale Semiconductor, Inc.
Slow Mode Divider
The slow mode divider is included to deliver a variable bus frequency to
the MCU in wait mode. The bus clocks are derived from the constant P
clock. The slow clock counter divides the P clock and E clock frequency
in powers of 2, up to 128. When the slow control register is cleared or
the part is not in wait mode, the slow mode divider is off and the bus
clocks frequency is not changed.
NOTE:
The clock monitor is clocked by the system clock (oscillator) reference;
the slow mode divider allows operation of the MCU at clock periods
longer than the clock monitor trigger time.
CGM Register Description
SLOW — Slow Mode Divider Register
Bit 7
6
5
4
0
0
0
0
RESET:
0
0
0
0
$00E0
3
2
1
Bit 0
0
SLDV2 SLDV1 SLDV0
0
0
0
0
SLDV2–SLDV0 — Slow Mode Divisor Selector Bits
The value 2 raised to the power indicated by these three bits, produce
the slow mode frequency divider. The range of the divider is 2 to 128
by steps of power of 2. When the bits are clear, the divider is
bypassed. Figure 19 shows the divider for all bit conditions and the
resulting bus rate for three example oscillator frequencies.
MC68HC912BD32 Rev 1.0
Clocks
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