MC68HC912BD32 Datasheet, PDF (246/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
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BDMACT — Background Mode Active Status
BDMACT becomes set as active BDM mode is entered so that the
BDM firmware ROM is enabled and put into the map. BDMACT is
cleared by a carefully timed store instruction in the BDM firmware as
part of the exit sequence to return to user code and remove the BDM
memory from the map. This bit has 4 clock cycles write delay.
0 = BDM is not active. BDM ROM and registers are not in map.
1 = BDM is active and waiting for serial commands. BDM ROM and
registers are in map
CAUTION:
The user should be careful that the state of the BDMACT bit is not unintentionally
changed with the WRITE_NEXT firmware command. If it is unintentionally changed
from 1 to 0, it will cause a system runaway because it would disable the BDM firmware
ROM while the CPU12 was executing BDM firmware. The following two commands
show how BDMACT may unintentionally get changed from 1 to 0.
WRITE_X with data $FEFE
WRITE_NEXT with data $C400
The first command writes the data $FEFE to the X index register. The second
command writes the data $C4 to the $FF00 INSTRUCTION register and also writes the
data $00 to the $FF01 STATUS register.
ENTAG — Tagging Enable
Set by the TAGGO command and cleared when BDM mode is
entered. The serial system is disabled and the tag function enabled
16 cycles after this bit is written.
0 = Tagging not enabled, or BDM active.
1 = Tagging active. BDM cannot process serial commands while
tagging is active.
SDV — Shifter Data Valid
Shows that valid data is in the serial interface shift register. Used by
the BDM firmware.
0 = No valid data. Shift operation is not complete.
1 = Valid Data. Shift operation is complete.
TRACE — Asserted by the TRACE1 command
MC68HC912BD32 Rev 1.0
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