MC68HC912BD32 Datasheet, PDF (133/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Standard Timer Module
Timer Registers
Timer Registers
Input/output pins default to general-purpose I/O lines until an internal
function which uses that pin is specifically enabled. The timer overrides
the state of the DDR to force the I/O state of each associated port line
when an output compare using a port line is enabled. In these cases the
data direction bits will have no affect on these lines.
When a pin is assigned to output an on-chip peripheral function, writing
to this PORTTn bit does not affect the pin but the data is stored in an
internal latch such that if the pin becomes available for general-purpose
output the driven level will be the last value written to the PORTTn bit.
TIOS — Timer Input Capture/Output Compare Select
Bit 7
6
5
4
3
IOS7
IOS6
IOS5
IOS4
IOS3
RESET:
0
0
0
0
0
2
IOS2
0
1
IOS1
0
Bit 0
IOS0
0
$0080
Read or write anytime.
IOS[7:0] — Input Capture or Output Compare Channel Configuration
0 = The corresponding channel acts as an input capture
1 = The corresponding channel acts as an output compare.
CFORC — Timer Compare Force Register
Bit 7
6
5
4
FOC7 FOC6 FOC5 FOC4
RESET:
0
0
0
0
3
FOC3
0
2
FOC2
0
1
FOC1
0
Bit 0
FOC0
0
$0081
Read anytime but will always return $00 (1 state is transient). Write
anytime.
FOC[7:0] — Force Output Compare Action for Channel 7-0
A write to this register with the corresponding data bit(s) set causes
the action which is programmed for output compare “n” to occur
immediately. The action taken is the same as if a successful
comparison had just taken place with the TCn register except the
interrupt flag does not get set.
3-timer
Standard Timer Module
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MC68HC912BD32 Rev 1.0