MC68HC912BD32 Datasheet, PDF (145/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Standard Timer Module
Timer Registers
PORTT — Timer Port Data Register
Bit 7
6
5
PT7
PT6
PT5
TIMER I/OC7 I/OC6 I/OC5
PA
PAI
4
PT4
I/OC4
3
PT3
I/OC3
2
PT2
I/OC2
1
PT1
I/OC1
Bit 0
PT0
I/OC0
$00AE
PORTT can be read anytime. When configured as an input, a read will
return the pin level. When configured as output, a read will return the
latched output data.
NOTE:
Writes do not change pin state when the pin is configured for timer
output. The minimum pulse width for pulse accumulator input should
always be greater than two module clocks due to input synchronizer
circuitry. The minimum pulse width for the input capture should always
be greater than the width of two module clocks due to input synchronizer
circuitry.
DDRT — Data Direction Register for Timer Port
Bit 7
6
5
4
3
DDT7 DDT6 DDT5 DDT4 DDT3
RESET:
0
0
0
0
0
2
DDT2
0
1
DDT1
0
Bit 0
DDT0
0
$00AF
Read or write anytime.
0 = Configures the corresponding I/O pin for input only
1 = Configures the corresponding I/O pin for output
The timer forces the I/O state to be an output for each timer port pin
associated with an enabled output compare. In these cases the data
direction bits will not be changed but have no affect on the direction
of these pins. The DDRT will revert to controlling the I/O direction of
a pin when the associated timer output compare is disabled. Input
captures do not override the DDRT settings.
15-timer
Standard Timer Module
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MC68HC912BD32 Rev 1.0