MC68HC912BD32 Datasheet, PDF (185/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
Functional Overview
To prepare a transmit message buffer for transmission the following
steps are required:
• Lock the corresponding message buffer in order to appear in the
Active Transmit Buffer window in the memory map.
• Wait for lock acknowledge.
• Write to the Active Transmit Buffer (ID, LEN, DATA). If no update
is needed, write is not required.
• Unlock the message buffer and clear the IFLG (buffer full) by
writing a ‘1’ to it.
NOTE:
Bit manipulation instructions (BSET or BCLR) shall not be used to clear
interrupt flags.
It is recommended to use one single instruction to clear the IFLG and to
unlock the buffer.
Synchronization
Process
The node can be configured as bus master. In this case the module
generates the periodic synchronization (SYNC) pulses. If the ALARM bit
is set, the master generates the ALARM pulses as long as this bit is
asserted. The ALARM bit is reset after 255ms - 256ms if it has not been
set again by the CPU within that period.
15-sibus
Byteflight™ Module
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MC68HC912BD32 Rev 1.0