MC68HC912BD32 Datasheet, PDF (208/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
TIME
CONFIGURATION
REGISTER 3 (TCR3)
The time configuration register 3 contains the specific programmable
time t_wx_delta for the node. Only a hard reset will clear the register.
TCR3
R
$xx04
W
HARDRESET
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
TWXD7* TWXD6* TWXD5* TWXD4* TWXD3* TWXD2*
0
0
0
0
0
0
Figure 41 Time Configuration Register 3 (TCR3)
BIT 1
TWXD1*
0
BIT 0
TWXD0*
0
TWXD7:TWXD0 — Time t_wx_delta
These bits contain the value for the time t_wx_delta as shown in
Table 49.
Table 49 Time t_wx_delta calculation
TWXD[7:0] t_wx_delta[ns]/25 - 1
NOTE: The TCR3 register can only be written if the SFTRES bit in the Module
Configuration register is set. The lower bound for TCR3 is 3.
Receive Interrupt
Status Register
(RISR)
The Receive Interrupt Status Register indicates the occurrence of
receive or SYNC pulse events, and together with the Receive Interrupt
Enable Register allows the module to operate in a polled or interrupt
driven system. Different interrupts can be generated. The Optical
Diagnosis Flag (OPTDF) is an indicator for the quality of the optical line
between two nodes. The OPTDF flag uses the internal error bit of the
optical transceiver which is driven on the Rx line when the photo stream
is below a certain level (see ELMOS E100.34 S/E module).
SYNAIF, SYNNIF, SLMMIF, XSYNIF and OPTDF are read and clear
only. RCVFIF and RXIF are read only. A flag can be cleared by writing a
1 to the corresponding bit position. Only one write is necessary to
request the clearing, i.e. the clear request is stored and executed as
soon as the condition which caused the setting is no longer valid. Writing
a 0 has no effect on the flag setting. Every flag has an associated
interrupt enable flag in the Receive Interrupt Enable Register. A hard or
soft reset will clear the register.
MC68HC912BD32 Rev 1.0
Byteflight™ Module
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