MC68HC912BD32 Datasheet, PDF (274/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Preliminary Electrical Characteristics
Table 78 Multiplexed Expansion Bus Timing
V_DD = 5.0 Vdc ± 5%, V_SS = 0 Vdc, T_A = T_L to T_H, unless otherwise noted
Num
Characteristic^{(1), (2), (3), (4)}
10 MHz
Delay Symbol
Min Max
Frequency of operation (E-clock frequency)
1 Cycle time
t_cyc = 1/f_o
2 Pulse width, E low
3 Pulse width, E high⁽⁵⁾
PW_EL = t_cyc/2 + delay
PW_EH = t_cyc/2 + delay
5 Address delay time
t_AD = t_cyc/4 + delay
7 Address valid time to ECLK rise t_AV = PW_EL − t_AD
8 Multiplexed address hold time t_MAH = t_cyc/4 + delay
9 Address Hold to Data Valid
10 Data Hold to High Z
11 Read data setup time
t_DHZ = t_AD − 20
12 Read data hold time
13 Write data delay time
14 Write data hold time
15 Write data setup time⁽⁵⁾
t_DSW = PW_EH − t_DDW
16 Read/write delay time
t_RWD = t_cyc/4 + delay
17 Read/write valid time to E rise t_RWV = PW_EL − t_RWD
18 Read/write hold time
19 Low strobe⁽⁷⁾ delay time
t_LSD = t_cyc/4 + delay
20 Low strobe⁽⁷⁾ valid time to E rise t_LSV = PW_EL − t_LSD
21 Low strobe⁽⁷⁾ hold time
22 Address access time⁽⁵⁾
23 Access time from E rise⁽⁵⁾
24 DBE delay from ECLK rise⁽⁵⁾
t_ACCA = t_cyc − t_AD − t_DSR
t_ACCE = PW_EH − t_DSR
t_DBED = t_cyc/4 + delay
25 DBE valid time
t_DBE = PW_EH − t_DBED
26 DBE hold time from ECLK fall
f_o
dc 10.0
—
t_cyc
100 —
−2
PW_EL
48
—
−2
PW_EH
48
—
29
t_AD
— 54
—
t_AV
0
—
−21
t_MAH
4
—
—
t_AHDS
30
—
—
t_DHZ
— 34
—
t_DSR
30 —
—
t_DHR
0
—
—
t_DDW
— 47
—
t_DHW
20 —
—
t_DSW
1
—
18
t_RWD
— 43
—
t_RWV
5
—
—
t_RWH
20 —
18
t_LSD
— 43
—
t_LSV
5
—
—
t_LSH
20 —
—
t_ACCA
—
16
—
t_ACCE
—
18
6
t_DBED
—
31
—
t_DBE
17 —
—
t_DBEH
0
10
1. All timings are calculated for normal port drives.
2. Crystal input is required to be within 45% to 55% duty.
3. Reduced drive must be off to meet these timings.
4. Unequalled loading of pins will affect relative timing numbers.
5. This characteristic is affected by clock stretch.
Add N × t_cyc where N = 0, 1, 2, or 3, depending on the number of clock stretches.
6. Equation still under evaluation
7. Without TAG enabled.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MC68HC912BD32 Rev 1.0
Preliminary Electrical Characteristics
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