MC68HC912BD32 Datasheet, PDF (109/292 Pages) Freescale Semiconductor, Inc – Advance Information

9-clock
Freescale Semiconductor, Inc.
Clocks
Clock Function Registers
0 = Clock monitor is disabled. Slow clocks and stop instruction may
be used.
1 = Slow or stopped clocks (including the stop instruction) will
cause a clock reset sequence.
FCME — Force Clock Monitor Enable
Write once in normal modes, anytime in special modes. Read
anytime.
In normal modes, when this bit is set, the clock monitor function
cannot be disabled until a reset occurs.
0 = Clock monitor follows the state of the CME bit.
1 = Slow or stopped clocks will cause a clock reset sequence.
In order to use both STOP and clock monitor, the CME bit should be
cleared prior to executing a STOP instruction and set after recovery
from STOP. If you plan on using STOP always keep FCME = 0.
FCM — Force Clock Monitor Reset
Writes are not allowed in normal modes, anytime in special modes.
Read anytime.
If DISR is set, this bit has no effect.
0 = Normal operation.
1 = Force a clock monitor reset (if clock monitor is enabled).
FCOP — Force COP Watchdog Reset
Writes are not allowed in normal modes; can be written anytime in
special modes. Read anytime.
If DISR is set, this bit has no effect.
0 = Normal operation.
1 = Force a COP reset (if COP is enabled).
DISR — Disable Resets from COP Watchdog and Clock Monitor
Writes are not allowed in normal modes, anytime in special modes.
Read anytime.
0 = Normal operation.
1 = Regardless of other control bit states, COP and clock monitor
will not generate a system reset.
Clocks
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MC68HC912BD32 Rev 1.0