MC68HC912BD32 Datasheet, PDF (209/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
Programmer’s Model
RISR
R
$xx06
W
H/S-RESET
BIT 7
RCVFIF
BIT 6
RXIF
BIT 5
SYNAIF
BIT 4
SYNNIF
BIT 3
SLMMIF
BIT 2
0
BIT 1
XSYNIF
0
0
0
0
0
0
0
Figure 42 Receive Interrupt Status Register (RISR)
BIT 0
OPTDF
0
RCVFIF — Receive FIFO Not Empty Interrupt Flag
This read-only bit will be set when the Receive FIFO is not empty. If
enabled, a FIFO not empty interrupt is pending while this flag is set.
The flag will be cleared if the FIFO is empty and when buffer 0 is
unlocked. The flag remains set if the FIFO is not empty.
1 = Receive FIFO is not empty.
0 = Receive FIFO is empty.
NOTE:
The RCVFIF flag is cleared two CPU cycles after unlocking buffer 0 if the
FIFO is empty, i.e. the application software should not read the RCVFIF
flag immediately after unlocking buffer 0.
RXIF — Receive Interrupt Flag
This read-only bit will be set when any of the enabled (IENAn = 1)
receive buffers has successfully received a message. It can be
cleared by clearing of the IFLG bit(s) of the corresponding buffer(s). If
RXIE is set, a receive interrupt is pending while this flag is set.
1 = At least one receive buffer is full.
0 = All receive buffers are empty.
NOTE:
The RXIF flag is cleared two CPU cycles after clearing of all IFLG bits,
i.e. the application software should not read the RXIF flag immediately
after clearing the IFLG bit(s).
SYNAIF — Synchronization Pulse ALARM Interrupt Flag
This bit will be set when a SYNC pulse ALARM has been received. If
enabled, a SYNC pulse interrupt is pending while this flag is set.
1 = SYNC pulse ALARM has been received.
0 = No SYNC pulse ALARM has occurred.
SYNNIF — Synchronization Pulse NORMAL Interrupt Flag
This bit will be set when a SYNC pulse NORMAL has been received.
If enabled, a SYNC pulse interrupt is pending while this flag is set.
39-sibus
Byteflight™ Module
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MC68HC912BD32 Rev 1.0