MC68HC912BD32 Datasheet, PDF (220/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
Byteflight™ Port
SBI Data Direction
Register (DDRSBI)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
DDRSBI R
0
DDRSBI7 DDRSBI6 DDRSBI5 DDRSBI4 DDRSBI3 DDRSBI2
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W
HARDRESET
0
0
0
0
0
0
0
Figure 54 Port SBI Data Direction Register (DDRSBI)
BIT 0
0
0
DDRSBI7 – DDRSBI2 — Data Direction Port SBI Bits
1 = Respective I/O pin is configured for output.
0 = Respective I/O pin is configured for input.
The Port SBI5–2 pins are outputs, if PMEREN, PSLMEN, PERREN,
PROKEN and PSYNEN are set, regardless of their corresponding
Data Direction Bits. Only a hard reset will clear the register.
Initialization
To ensure correct operation, use the following initialization procedure:
• Enter the soft reset mode by setting the SFTRES bit (MCR)
• Desired setting of module configuration register (MCR) – Master
or Slave select, MASTER bit
• Desired setting of the FIFO Size register (FSIZR) – configure FIFO
size, FSIZ4:0 bits
• Desired setting of time configuration registers (TCR1–TCR3)
• Desired setting of the message buffer control registers
(BUFCTL15..0) – configure the buffers as transmit or receive
buffers
– enable/disable of the corresponding interrupt, IENA bits
• Set FIFO acceptance register (FIDAC) and mask register
(FIDMR).
• Exit the soft reset mode by resetting the SFTRES bit (MCR)
MC68HC912BD32 Rev 1.0
Byteflight™ Module
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