MC68HC912BD32 Datasheet, PDF (45/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Registers
Introduction
Table 9 MC68HC912BD32 Register Map (Sheet 9 of 9)
Address Bit 7
6
5
4
3
2
1
Bit 0
Name
$0149
D7
D6
D5
D4
D3
D2
D1
D0
DATA7
$014A
D7
D6
D5
D4
D3
D2
D1
D0
DATA8
$014B
D7
D6
D5
D4
D3
D2
D1
D0
DATA9
$014C
D7
D6
D5
D4
D3
D2
D1
D0
DATA10
$014D
D7
D6
D5
D4
D3
D2
D1
D0
DATA11
$014E-$
014F
-
-
-
-
-
-
-
-
Reserved
$0150 IFLG
IENA LOCK
0
0
0
0
CFG BUFCTL0
$0151 IFLG
IENA LOCK
0
0
0
0
CFG BUFCTL1
$0152 IFLG
IENA LOCK
0
0
0
0
CFG BUFCTL2
$0153 IFLG
IENA LOCK
0
0
0
0
CFG BUFCTL3
$0154 IFLG
IENA LOCK
0
0
0
0
CFG BUFCTL4
$0155 IFLG
IENA LOCK
0
0
0
0
CFG BUFCTL5
$0156 IFLG
IENA LOCK
0
0
0
0
CFG BUFCTL6
$0157 IFLG
IENA LOCK
0
0
0
0
CFG BUFCTL7
$0158 IFLG
IENA LOCK
0
0
0
0
CFG BUFCTL8
$0159 IFLG
IENA LOCK
0
0
0
0
CFG BUFCTL9
$015A IFLG
IENA LOCK
0
0
0
0
CFG BUFCTL10
$015B IFLG
IENA LOCK
0
0
0
0
CFG BUFCTL11
$015C IFLG
IENA LOCK
0
0
0
0
CFG BUFCTL12
$015D IFLG
IENA LOCK
0
0
0
0
CFG BUFCTL13
$015E IFLG
IENA LOCK
0
0
0
0
CFG BUFCTL14
$015F IFLG
IENA LOCK
0
0
0
0
CFG BUFCTL15
1. Port A, port B, and data direction registers DDRA and DDRB are not in map in expanded and peripheral modes.
2. Port E and DDRE not in map in peripheral mode; also not in map in expanded modes with EME set.
3. Not in map in peripheral mode.
4. $0120-$012D: Byteflight™ Active Transmit Buffer Register
5. $0130-$013D: Byteflight™ Active Receive Buffer Register
6. $0140-$014D: Byteflight™ Active FIFO Register
9-reg
MC68HC912BD32 Rev 1.0
Registers
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