MC68HC912BD32 Datasheet, PDF (110/292 Pages) Freescale Semiconductor, Inc – Advance Information

Clocks
Freescale Semiconductor, Inc.
CR2, CR1, CR0 — COP Watchdog Timer Rate Select Bits
The COP system is driven by a constant frequency of E/2¹³. (RTBYP
in the RTICTL register allows all but two stages of this divider to be
bypassed for testing in special modes only.) These bits specify an
additional division factor to arrive at the COP time-out rate (the clock
used for this module is the E clock).
Write once in normal modes, anytime in special modes. Read
anytime.
Table 22 COP Watchdog Rates (RTBYP = 0)
CR2
0
0
0
0
1
1
1
1
CR1
0
0
1
1
0
0
1
1
CR0
0
1
0
1
0
1
0
1
Divide E
By:
OFF
2¹³
2¹⁵
2¹⁷
2¹⁹
2²¹
2²²
2²³
At E = 4.0 MHz
Time-Out
–0 to +2.048 s
OFF
2.048 ms
8.192 ms
32.768 ms
131.072 ms
524.288 ms
1.048 s
2.097 s
At E = 8.0 MHz
Time-Out
–0 to +1.024 s
OFF
1.024 ms
4.096 ms
16.384 ms
65.536 ms
262.144 ms
524.288 ms
1.048576 s
At E = 10.0 MHz
Time-Out
–0 to +838.861 ms
OFF
0.819 ms
3.277 ms
13.107 ms
52.429 ms
209.715 ms
419.430 ms
838.861 ms
COPRST — Arm/Reset COP Timer Register
$0017
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
RESET:
0
0
0
0
0
0
0
0
Always reads $00.
Writing $55 to this address is the first step of the COP watchdog
sequence.
Writing $AA to this address is the second step of the COP watchdog
sequence. Other instructions may be executed between these writes
but both must be completed in the correct order prior to time-out to
avoid a watchdog reset. Writing anything other than $55 or $AA
causes a COP reset to occur.
MC68HC912BD32 Rev 1.0
Clocks
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Go to: www.freescale.com
10-clock