MC68HC912BD32 Datasheet, PDF (164/292 Pages) Freescale Semiconductor, Inc – Advance Information

Serial Interface
Freescale Semiconductor, Inc.
SP0CR1 — SPI Control Register 1
Bit 7
6
5
SPIE
SPE SWOM
RESET:
0
0
0
4
MSTR
0
3
CPOL
0
2
CPHA
1
1
SSOE
0
Bit 0
LSBF
0
$00D0
Read or write anytime.
SPIE — SPI Interrupt Enable
1 = Hardware interrupt sequence is requested each time the SPIF
or MODF status flag is set
0 = SPI interrupts are inhibited
SPE — SPI System Enable
0 = SPI internal hardware is initialized and SPI system is in a
low-power disabled state.
1 = PS[4:7] are dedicated to the SPI function
When MODF is set, SPE always reads zero. SP0CR1 must be written
as part of a mode fault recovery sequence.
SWOM — Port S Wired-OR Mode
Controls not only SPI output pins but also the general-purpose output
pins (PS[4:7]) which are not used by SPI.
0 = SPI and/or PS[4:7] output buffers operate normally
1 = SPI and/or PS[4:7] output buffers behave as open-drain
outputs
MSTR — SPI Master/Slave Mode Select
0 = Slave mode
1 = Master mode
CPOL, CPHA — SPI Clock Polarity, Clock Phase
These two bits are used to specify the clock format to be used in SPI
operations. When the clock polarity bit is cleared and data is not being
transferred, the SCK pin of the master device is low. When CPOL is
set, SCK idles high. See Figure 22 and Figure 23.
SSOE — Slave Select Output Enable
The SS output feature is enabled only in the master mode by
asserting the SSOE and DDS7.
MC68HC912BD32 Rev 1.0
Serial Interface
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18-sint