MC68HC912BD32 Datasheet, PDF (189/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
Functional Overview
Table 38 Module Interrupt Vectors
Function
High priority SYNC
pulse interrupt
FIFO Not Empty
Interrupt
Receive Interrupt
Synchronization
Interrupt
General
Interrupt
Source
XSYNIF
RCVFIF
IFLG [15..0] (RX)
SYNAIF
SYNNIF
IFLG [15..0] (TX)
OVRNIF
ERRIF
SYNEIF
SYNLIF
ILLPIF
WAKEIF
LOCKIF
SLMMIF
Local
Mask
XSYNIE
RCVFIE
IENA [15:0]
SYNAIE
SYNNIE
IENA [15:0]
OVRNIE
ERRIE
SYNEIE
SYNLIE
ILLPIE
WAKEIE
LOCKIE
SLMMIE
Global
Mask
X Bit⁽¹⁾
I Bit⁽²⁾
1. The X Bit in the condition code register (CCR) is the interrupt mask for the XIRQ pin
2. The I Bit in the condition code register (CCR) is the global interrupt mask for all HC12 CPU
interrupts.
NOTE: Bit manipulation instructions (BSET or BCLR) shall not be used to clear
interrupt flags.
Wakeup
The serial bus interface module is able to wake-up from CPU STOP
mode or Module SLEEP mode by the recognition of a falling edge at the
input Rx. The local mask for the wakeup interrupt is the Wakeup
Interrupt Enable bit (WAKEIE). After wake-up a node configured as
Master should start to send SYNC pulses during tsl_min (refer to
transceiver spec ELMOS 100.34) in order to avoid that the transceiver
enters sleep mode again.
19-sibus
Byteflight™ Module
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MC68HC912BD32 Rev 1.0