MC68HC912BD32 Datasheet, PDF (204/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
Module
Configuration
Register (MCR)
MCR R
$xx00 W
HARDRESET
BIT 7
SFTRES
1
BIT 6
MASTER*
0
BIT 5
ALARM
0
BIT 4
SLPAK
0
BIT 3
SLPRQ
0
BIT 2
WPULSE*
0
Figure 36 General Configuration Register (MCR)
BIT 1
SSWAI
0
BIT 0
0
0
NOTE:
Setting SFTRES and writing to other bits in the MCR can be done in
separate instructions only! Trying to set SFTRES and change other bits
together will change the SFTRES only, the other bits will be unchanged.
Clearing SFTRES and writing to other bits in the MCR can be done in
one instruction.
SFTRES — Soft Reset
When this bit is set by the CPU, the module immediately enters the
soft reset state. Any ongoing transmission or reception is aborted and
synchronization to the bus is lost.
When this bit is cleared by the CPU, the interface will start to connect
back to the bus. It will be synchronized after the next SYNC pulse on
the bus.
1 = Soft reset state.
0 = Normal operation.
MASTER — Master Select
This bit selects the node as bus master or as bus slave. Writing to this
bit is allowed during soft reset only.
1 = The interface is a master and generates the SYNC pulses.
0 = The interface is a slave and verifies the SYNC pulses.
ALARM — Master Alarm Pulses
If the Master bit and the Alarm bit are set, ALARM pulses are
transmitted.
1 = The interface generates ALARM pulses.
0 = The interface generates normal SYNC pulses.
The ALARM bit is reset after 255ms - 256ms if it has not been set
again by the CPU within that period. The Alarm bit can be set and
cleared any time.
MC68HC912BD32 Rev 1.0
Byteflight™ Module
For More Information On This Product,
Go to: www.freescale.com
34-sibus