MC68HC912BD32 Datasheet, PDF (120/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Pulse Width Modulator
PPOL3 — PWM Channel 3 Polarity
0 = Channel 3 output is low at the beginning of the period; high
when the duty count is reached.
1 = Channel 3 output is high at the beginning of the period; low
when the duty count is reached.
PPOL2 — PWM Channel 2 Polarity
0 = Channel 2 output is low at the beginning of the period; high
when the duty count is reached.
1 = Channel 2 output is high at the beginning of the period; low
when the duty count is reached.
PPOL1 — PWM Channel 1 Polarity
0 = Channel 1 output is low at the beginning of the period; high
when the duty count is reached.
1 = Channel 1 output is high at the beginning of the period; low
when the duty count is reached.
PPOL0 — PWM Channel 0 Polarity
0 = Channel 0 output is low at the beginning of the period; high
when the duty count is reached.
1 = Channel 0 output is high at the beginning of the period; low
when the duty count is reached.
NOTE:
Register bits PCLK0 to PCLK3 may be written anytime. If a clock select
is changed while a PWM signal is being generated, a truncated or
stretched pulse may occur during transition.
NOTE:
Depending on the polarity bit, the duty registers may contain the count
of either the high time or the low time. If the polarity bit is one, the output
starts high and then goes low when the duty count is reached, so the
duty registers contain a count of the high time. If the polarity bit is zero,
the output starts low and then goes high when the duty count is reached,
so the duty registers contain a count of the low time.
MC68HC912BD32 Rev 1.0
Pulse Width Modulator
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8-pwm