MC68HC912BD32 Datasheet, PDF (268/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Preliminary Electrical Characteristics
Table 76 Control Timing
Characteristic
Frequency of operation
E-clock period
Crystal frequency
External oscillator frequency
Processor control setup time t_PCSU = t_cyc/2+ 20
Reset input pulse width
To guarantee external reset vector
Minimum input time (can be preempted by internal reset)
Mode programming setup time
Mode programming hold time
Interrupt pulse width, IRQ edge-sensitive mode
PW_IRQ = 2t_cyc + 20
Wait recovery startup time
t_WRS = 4t_cyc
Timer input capture pulse width PW_TIM = 2t_cyc + 20
Pulse accumulator pulse width
Symbol
f_o
t_cyc
f_XTAL
4f_o
t_PCSU
PW_RSTL
t_MPS
t_MPH
PW_IRQ
t_WRS
PW_TIM
PW_PA
10.0 MHz
Min Max
dc 10.0
100 —
— 40.0
dc 40.0
70 —
32 —
2
—
4
—
10 —
220 —
—
220
TBD
TBD
—
—
Unit
MHz
ns
MHz
MHz
ns
t_cyc
t_cyc
t_cyc
ns
ns
t_cyc
ns
ns
1. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives
the pin low for 16 clock cycles, releases the pin, and samples the pin level 8 cycles later
to determine the source of the interrupt.
PT[7:0]¹
PT[7:0]²
PW_TIM
PT7¹
PT7²
PW_PA
NOTES:
1. Rising edge sensitive input
2. Faling edge sensitive input
Figure 59 Timer Inputs
MC68HC912BD32 Rev 1.0
Preliminary Electrical Characteristics
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