MC68HC912BD32 Datasheet, PDF (72/292 Pages) Freescale Semiconductor, Inc – Advance Information

Flash EEPROM
Freescale Semiconductor, Inc.
FSTE — Stress Test Enable
0 = Disables the gate/drain stress circuitry
1 = Enables the gate/drain stress circuitry
GADR — Gate/Drain Stress Test Select
0 = Selects the drain stress circuitry
1 = Selects the gate stress circuitry
HVT — Stress Test High Voltage Status
0 = High voltage not present during stress test
1 = High voltage present during stress test
FENLV — Enable Low Voltage
0 = Disables low voltage transistor in current reference circuit
1 = Enables low voltage transistor in current reference circuit
FDISVFP — Disable Status V_FP Voltage Lock
When the V_FP pin is below normal programming voltage the Flash
module will not allow writing to the LAT bit; the user cannot erase or
program the Flash module. The FDISVFP control bit enables writing
to the LAT bit regardless of the voltage on the V_FP pin.
0 = Enable the automatic lock mechanism if V_FP is low
1 = Disable the automatic lock mechanism if V_FP is low
VTCK — V_T Check Test Enable
When VTCK is set, the Flash EEPROM module uses the V_FP pin to
control the control gate voltage; the sense amp time-out path is
disabled. This allows for indirect measurements of the bit cells
program and erase threshold. If V_FP < V_ZBRK (breakdown voltage) the
control gate will equal the V_FP voltage.
If V_FP > V_ZBRK the control gate will be regulated by the following
equation:
Vcontrol gate = V_ZBRK + 0.44 × (V_FP − V_ZBRK)
0 = V_T test disable
1 = V_T test enable
MC68HC912BD32 Rev 1.0
Flash EEPROM
For More Information On This Product,
Go to: www.freescale.com
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