MC68HC912BD32 Datasheet, PDF (115/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Pulse Width Modulator
Introduction
Clock Source
(E or Scaled E)
GATE
(clock edge sync)
PWCNTx
reset
CENTR=0
up/down
(duty cycle)
8-bit Compare =
PWDTYx
(period)
8-bit Compare =
PWPERx
PWENx
Sync
PPOL=0
PPOL=1
PWDTY
PWPER
From Port P
Data Register
S QM
U
QX
R
M
U
X _{To Pin}
Driver
PPOLx
Figure 15 Block Diagram of PWM Left-Aligned Output Channel
3-pwm
Pulse Width Modulator
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MC68HC912BD32 Rev 1.0