MC68HC912BD32 Datasheet, PDF (276/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Preliminary Electrical Characteristics
Table 79 SPI Timing
(V_DD = 5.0 Vdc ±5%, V_SS = 0 Vdc, T_A = T_L to T_H , 200 pF load on all SPI pins)⁽¹⁾
Num
Function
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
f_op
DC
DC
1/2
1/2
E-clock
frequency
SCK Period
Master
Slave
Enable Lead Time
Master
Slave
Enable Lag Time
Master
Slave
Clock (SCK) High or Low Time
Master
Slave
Sequential Transfer Delay
Master
Slave
Data Setup Time (Inputs)
Master
Slave
t_sck
2
256
t_cyc
2
—
t_cyc
t_lead
1/2
1
—
t_sck
—
t_cyc
t_lag
1/2
—
t_sck
1
—
t_cyc
t_wsck
t_cyc − 60 128 t_cyc
ns
t_cyc − 30
—
ns
t_td
1/2
—
t_sck
1
—
t_cyc
t_su
30
—
ns
30
—
ns
Data Hold Time (Inputs)
Master
Slave
t_hi
0
—
ns
30
—
ns
Slave Access Time
Slave MISO Disable Time
Data Valid (after SCK Edge)
Master
Slave
t_a
—
t_dis
—
1
t_cyc
1
t_cyc
t_v
—
50
ns
—
50
ns
Data Hold Time (Outputs)
Master
Slave
t_ho
0
—
ns
0
—
ns
Rise Time
Input
Output
t_ri
—
t_cyc − 30
ns
t_ro
—
30
ns
Fall Time
Input
Output
t_fi
—
t_cyc − 30
ns
t_fo
—
30
ns
1. All AC timing is shown with respect to 20% V_DD and 70% V_DD levels unless otherwise noted.
MC68HC912BD32 Rev 1.0
Preliminary Electrical Characteristics
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