MC68HC912BD32 Datasheet, PDF (213/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
Programmer’s Model
Receive Interrupt
Enable Register
(RIER)
The Receive Interrupt Enable Register allows to enable/disable the
different receive or SYNC pulse interrupt sources for different interrupt
requests. A hard or soft reset will clear the register.
RIER
R
$xx08
W
H/S-RESET
BIT 7
RCVFIE
BIT 6
RXIE
BIT 5
SYNAIE
BIT 4
SYNNIE
BIT 3
SLMMIE
BIT 2
0
BIT 1
XSYNIE
0
0
0
0
0
0
0
Figure 44 Receive Interrupt Enable Register (RIER)
BIT 0
0
0
RCVFIE — Receive FIFO Not Empty Interrupt Enable
1 = A Receive FIFO not empty event will result in a receive FIFO
not empty interrupt.
0 = No interrupt will be generated from this event.
RXIE — Receive Interrupt Enable
1 = A receive event will result in a receive interrupt.
0 = No interrupt will be generated from this event.
SYNAIE — Synchronization Pulse ALARM Interrupt Enable
1 = A SYNC pulse ALARM event will result in a SYNC pulse
interrupt.
0 = No interrupt will be generated from this event.
SYNNIE — Synchronization Pulse NORMAL Interrupt Enable
1 = A SYNC pulse NORMAL event will result in a SYNC pulse
interrupt.
0 = No interrupt will be generated from this event.
SLMMIE — Slot Mismatch Interrupt Enable
1 = A slot mismatch event will result in a general interrupt.
0 = No interrupt will be generated from this event.
XSYNIE — Xsync Pulse Interrupt Enable
1 = A SYNC pulse event will result in an XSYNC pulse interrupt.
0 = No interrupt will be generated from this event.
43-sibus
Byteflight™ Module
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MC68HC912BD32 Rev 1.0