MC68HC912BD32 Datasheet, PDF (142/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Standard Timer Module
Depending on the TIOS bit for the corresponding channel, these
registers are used to latch the value of the free-running counter when
a defined transition is sensed by the corresponding input capture
edge detector or to trigger an output action for output compare.
Read anytime. Write anytime for output compare function. Writes to
these registers have no meaning or effect during input capture. All
timer input capture/output compare registers are reset to $0000.
PACTL — Pulse Accumulator Control Register
$00A0
Bit 7
6
5
4
3
2
1
Bit 0
0
PAEN PAMOD PEDGE CLK1 CLK0 PAOVI
PAI
RESET:
0
0
0
0
0
0
0
0
Read or write anytime.
PAEN — Pulse Accumulator System Enable
0 = Pulse Accumulator system disabled
1 = Pulse Accumulator system enabled
PAEN is independent from TEN.
PAMOD — Pulse Accumulator Mode
0 = Event counter mode
1 = Gated time accumulation mode
PEDGE — Pulse Accumulator Edge Control
For PAMOD = 0 (event counter mode)
0 = Falling edges on the pulse accumulator input pin (PT7/PAI)
cause the count to be incremented
1 = Rising edges on the pulse accumulator input pin cause the
count to be incremented
For PAMOD = 1 (gated time accumulation mode)
0 = Pulse accumulator input pin high enables E÷64 clock to pulse
accumulator and the trailing falling edge on the pulse
accumulator input pin sets the PAIF flag.
1 = Pulse accumulator input pin low enables E÷64 clock to pulse
accumulator and the trailing rising edge on the pulse
accumulator input pin sets the PAIF flag.
MC68HC912BD32 Rev 1.0
Standard Timer Module
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