MC68HC912BD32 Datasheet, PDF (71/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Flash EEPROM
Flash EEPROM Registers
Flash EEPROM Registers
FEELCK — Flash EEPROM Lock Control Register
$00F4
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
LOCK
RESET:
0
0
0
0
0
0
0
0
In normal modes the LOCK bit can only be written once after reset.
LOCK — Lock Register Bit
0 = Enable write to FEEMCR register
1 = Disable write to FEEMCR register
FEEMCR — Flash EEPROM Module Configuration Register
Bit 7
6
5
4
3
2
0
0
0
0
0
0
RESET:
0
0
0
0
0
0
$00F5
1
Bit 0
0
BOOTP
0
1
This register controls the operation of the Flash EEPROM array. BOOTP
cannot be changed when the LOCK control bit in the FEELCK register is
set or if ENPE in the FEECTL register is set.
BOOTP — Boot Protect
The boot block is located at $7800–$7FFF or $F800–$FFFF
depending upon the mapped location of the Flash EEPROM array
and mask set ($7C00–$7FFF or $FC00–$FFFF for 1K byte block).
0 = Enable erase and program of 1K byte or 2K byte boot block
1 = Disable erase and program of 1K byte or 2K byte boot block
FEETST — Flash EEPROM Module Test Register
Bit 7
6
5
4
FSTE
GADR
HVT
FENLV
RESET:
0
0
0
0
3
FDISVFP
0
2
VTCK
0
1
STRE
0
$00F6
Bit 0
MWPR
0
In normal mode, writes to FEETST control bits have no effect and always
read zero. The Flash EEPROM module cannot be placed in test mode
inadvertently during normal operation.
3-flash
Flash EEPROM
For More Information On This Product,
Go to: www.freescale.com
MC68HC912BD32 Rev 1.0