MC68HC912BD32 Datasheet, PDF (155/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Interface
Serial Communication Interface (SCI)
TE — Transmitter Enable
0 = Transmitter disabled
1 = SCI transmit logic is enabled and the TXD pin (Port S bit 1) is
dedicated to the transmitter. The TE bit can be used to queue
an idle preamble.
RE — Receiver Enable
0 = Receiver disabled
1 = Enables the SCI receive circuitry
RWU — Receiver Wake-Up Control
0 = Normal SCI Receiver
1 = Enables the wake-up function and inhibits further receiver
interrupts. Normally hardware wakes the receiver by
automatically clearing this bit.
SBK — Send Break
0 = Break generator off
1 = Generate a break code (at least 10 or 11 contiguous zeros)
As long as SBK remains set the transmitter will send zeros. When
SBK is changed to zero, the current frame of all zeros is finished
before the TxD line goes to the idle state. If SBK is toggled on and off,
the transmitter will send 10 (or 11) zeros and then revert to mark idle
or sending data.
SC0SR1 — SCI Status Register 1
$00C4
Bit 7
6
5
4
3
2
1
Bit 0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
RESET:
1
1
0
0
0
0
0
0
The bits in these registers are set by various conditions in the SCI
hardware and are automatically cleared by special acknowledge
sequences. The receive related flag bits in SC0SR1 (RDRF, IDLE,
OR, NF, FE, and PF) are all cleared by a read of the SC0SR1 register
followed by a read of the transmit/receive data register L. However,
only those bits which were set when SC0SR1 was read will be cleared
by the subsequent read of the transmit/receive data register L. The
9-sint
MC68HC912BD32 Rev 1.0
Serial Interface
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