MC68HC912BD32 Datasheet, PDF (63/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Bus Control and Input/Output
Registers
This register is not in the map in peripheral mode or expanded modes
when the EME bit is set.
Read and write anytime.
DDRE — Port E Data Direction Register
Bit 7
6
5
4
3
2
1
DDE7
DDE6
DDE5
DDE4
DDE3
DDE2
0
RESET:
0
0
0
0
0
0
–
$0009
Bit 0
0
–
This register determines the primary direction for each port E pin
configured as general-purpose I/O.
0 = Associated pin is a high-impedance input
1 = Associated pin is an output
PE[1:0] are associated with XIRQ and IRQ and cannot be configured as
outputs. These pins can be read regardless of whether the alternate
interrupt functions are enabled.
This register is not in the map in peripheral mode and expanded modes
while the EME control bit is set.
Read and write anytime.
PEAR — Port E Assignment Register
Bit 7
6
5
4
3
2
1
NDBE
0
PIPOE NECLK LSTRE RDWE
0
RESET:
0
–
0
0
0
0
–
RESET:
0
–
1
0
1
1
–
RESET:
1
–
0
1
0
0
–
RESET:
1
–
0
1
0
0
–
RESET:
0
–
1
0
1
1
–
Bit 0
0
–
–
–
–
–
$000A
Normal
Expanded
Special
Expanded
Peripheral
Normal
Single Chip
Special
Single Chip
The PEAR register is used to choose between the general-purpose I/O
functions and the alternate bus control functions of port E. When an
5-bus
Bus Control and Input/Output
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MC68HC912BD32 Rev 1.0