MC68HC912BD32 Datasheet, PDF (116/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Pulse Width Modulator
Clock Source
(E or Scaled E)
GATE
PWCNTx
(clock edge sync) up/down
CENTR=1
reset
(duty cycle)
8-bit Compare =
PWDTYx
(period)
8-bit Compare =
PWPERx
PWENx
Sync
PPOL= 1 0
From Port P
Data Register
T QM
U
QX
M
U
X _{To Pin}
Driver
PPOLx
PPOL= 0 1
PWDTY
(PWPER–PWDTY)*2
Period = PWPER*2
PWDTY
Figure 16 Block Diagram of PWM Center-Aligned Output Channel
MC68HC912BD32 Rev 1.0
Pulse Width Modulator
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4-pwm