MC68HC912BD32 Datasheet, PDF (200/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
Receive and
Transmit Message
Buffers
There are 16 configurable message buffers, consisting of 14 bytes each.
The organization of one message buffer is shown in Figure 34. The first
byte contains the 8-bit identifier (ID), the second byte contains the length
(LEN) byte (the 4 msb are reserved), followed by a maximum of 12 data
bytes (DATA0..11) and two reserved bytes. A LEN value greater than 12
will be transmitted and used in the CRC calculation of transmitter and
receiver, but the stored LEN value in the receive buffer will be 12.
The message buffers are configurable as receive, receive FIFO or
transmit buffers. The receive and receive FIFO buffer system starts with
message buffer 0 and can be configured to the maximum of all 16
message buffers (no transmit buffer). The transmit buffer system starts
with message buffer 15 and can be configured to the maximum of all 16
message buffers (no receive buffer).
NOTE: No mixing of receiver, FIFO or transmit buffers is allowed.
Only the ‘active’ buffers (transmit buffer, receive buffer and receive FIFO
buffer) are addressable by the CPU and allocate 14 bytes each in the
memory map. The ‘non-active’ buffers do not appear in the memory
map. To activate a buffer the buffer must be locked. Only one transmit
buffer, one receive buffer and one receive FIFO buffer may be locked at
a time. A locking error interrupt flag is set and if enabled a locking
interrupt is generated when the CPU tries to lock two buffers of the same
type.
MC68HC912BD32 Rev 1.0
Byteflight™ Module
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