MC68HC912BD32 Datasheet, PDF (33/292 Pages) Freescale Semiconductor, Inc – Advance Information

Port AD
Port P
Port T
13-pins
Freescale Semiconductor, Inc.
Pinout and Signal Descriptions
Port Signals
Input to the analog-to-digital subsystem and general-purpose input.
When analog-to-digital functions are not enabled, the port has eight
general-purpose input pins, PAD[7:0]. The ADPU bit in the ATDCTL2
register enables the A/D function.
Port AD pins are inputs; no data direction register is associated with this
port. The port has no resistive input loads and no reduced drive controls.
Refer to Analog to Digital Converter.
The four pulse-width modulation channel outputs share general-purpose
port P pins. The PWM function is enabled with the PWEN register.
Enabling PWM pins takes precedence over the general-purpose port.
When pulse-width modulation is not in use, the port pins may be used
for general-purpose I/O.
Register DDRP determines pin direction of port P when used for
general-purpose I/O. When DDRP bits are set, the corresponding pin is
configured for output. On reset the DDRP bits are cleared and the
corresponding pin is configured for input.
When the PUPP bit in the PWCTL register is set, all input pins are pulled
up internally by an active pull-up device. Pullups are disabled after reset.
Setting the RDPP bit in the PWCTL register configures all port P outputs
to have reduced drive levels. Levels are at normal drive capability after
reset. The PWCTL register can be read or written anytime after reset.
Refer to Pulse Width Modulator.
This port provides eight general-purpose I/O pins when not enabled for
input capture and output compare in the timer and pulse accumulator
subsystem. The TEN bit in the TSCR register enables the timer function.
The pulse accumulator subsystem is enabled with the PAEN bit in the
PACTL register.
Register DDRT determines pin direction of port T when used for
general-purpose I/O. When DDRT bits are set, the corresponding pin is
configured for output. On reset the DDRT bits are cleared and the
corresponding pin is configured for input.
Pinout and Signal Descriptions
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MC68HC912BD32 Rev 1.0