MC68HC912BD32 Datasheet, PDF (25/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Pinout and Signal Descriptions
Signal Descriptions
EXTAL
MCU
XTAL _NC
4 x E (DIVBYP=0)
2 x E (DIVBYP=1)
CMOS-COMPATIBLE
EXTERNAL OSCILLATOR
E-Clock Output
(ECLK)
Figure 5 External Oscillator Connections
XTAL is the crystal output.The XTAL pin must be left unterminated when
an external CMOS compatible clock input is connected to the EXTAL
pin. The XTAL output is normally intended to drive only a crystal. The
XTAL output can be buffered with a high-impedance buffer to drive the
EXTAL input of another device.
In all cases take extra care in the circuit board layout around the
oscillator pins. Load capacitances shown in the oscillator circuits include
all stray layout capacitances. Refer to Figure 4 and Figure 5 for
diagrams of oscillator circuits.
ECLK is the output connection for the internal bus clock and is used to
demultiplex the address and data and is used as a timing reference.
ECLK frequency is equal to 1/4 the crystal frequency out of reset (in
normal operation with DIVBYP=0, refer to Clock Divider Bypass
(DIVBYP)).
In normal single-chip mode the E-clock output is off at reset to reduce
the effects of RFI, but can be turned on if necessary.
In special single-chip mode the E-clock output is on at reset but can be
turned off.
In special peripheral mode the E clock is an input to the MCU.
All clocks, including the E clock, are halted when the MCU is in STOP
mode. It is possible to configure the MCU to interface to slow external
memory. ECLK can be stretched for such accesses.
5-pins
Pinout and Signal Descriptions
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MC68HC912BD32 Rev 1.0